Many electronic devices include a set of basic components for processing information, namely, a central processing unit (CPU) 10 and a memory unit 12. FIGS. 1 and 2 show a typical CPU 10 and memory interface. Conventionally, the CPU 10 accesses the memory unit 12 by supplying addressing signals, memory requests and read/write control signals. As shown in FIG. 1, the address lines from the CPU 10 provide the address information in the form of addressing signals to be decoded by the memory unit 12. The control lines from the CPU 10 provide the memory request and the read/write signals to the memory unit 12. The memory unit 12 generally includes a memory cell array 14 which can be arranged in a 1, 2, or 3-dimensional structure. For a 2-dimensional array structure, the memory cells can be arranged in a number of rows and columns. Each cell of the memory unit 12 can be implemented to accommodate various size data, for example, bit, nibble, byte, word, etc. Generally, a memory unit 12 can be a RAM, ROM, EEPROM, FLASH, or some other type of memory structure as is known in the art. A memory unit 12, in addition to having memory cells, contains an address decode unit 16 which generally consists of a row decode block 18 and a column decode block 20. The CPU 10, in conjunction with the address decode unit, can uniquely address any memory cell location within the memory cell array 14. A memory access can be implemented by using the address decode unit to decode the address information received from the CPU 10 and thereby cause one row select signal and one column select signal to be asserted. Hence, any particular memory cell can be selectably addressable and accessed by a particular row/column pair of select signals.
As mentioned above, the control lines from the CPU 10 include a read/write signal and a memory request signal. The control signals indicate the operation of reading from or writing to an addressable memory cell unit within the memory unit 12. For example, if the read/write signal indicates a "read", then data is transferred using the data lines from memory unit 12 to the CPU 10, and if the read/write signal indicates a "write" signal then data is transferred from the CPU 10 to the memory unit 12. As shown in FIG. 1, data can be transferred using the data lines from the CPU 10 to the memory unit 12 and vice versa.
It is important to note that with each memory access, both the row decode block 18 and column decode block 20 are active and performing power-consuming transitioning operations within the circuitry of the respective blocks. As the CPU 10 executes a program from memory, the address lines feeding the row/column decode blocks 20 change with each memory access. As address lines change, transistor switching occurs within the address decode logic (not shown) of the address decode unit 16. The transistor switching causes power to be consumed. In other words, power is consumed with each memory access as a result of address decoding. In addition, power is consumed by driving the address lines from the CPU 10 to the memory unit 12 and any peripheral modules.
FIG. 3 is a schematic representation of an electronic device 22, wherein a CPU 10 and a plurality of memory units 10 and peripheral modules 13 are utilized. As shown in FIG. 3, it is evident that the multiplication of memory units 10 and peripheral modules 13 in an electronic device results in further increase in power consumption and reduction in the speed of information transfer/processing in the electronic device 22.
Thus, there is a need to provide a more power-efficient, faster, and robust memory access in electronic devices by reducing the frequency of driving the address lines and propagating addressing signals through decode logic of memory units.